Keyword: logic analyzer

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BAD BAD 127 / 128 transition

Optimized ISR runtime - 8th pulse

Optimized sampling-ISR runtime

Optimized ISR runtime - 1st pulse

1st optimization attempt - 8th pulse

1st optimization attempt - 1st pulse

1st optimization attempt

Starting values - 8th pulse

Starting values - 1st pulse

Starting values - overview

Fully interrupt driven soft-uart receiver

Fully interrupt driven soft-uart receiver

Fully interrupt driven soft-uart receiver on an AT…

Debugging avrdude - arduino.c

Preparations for brain surgery

Preparations for brain surgery

The patient is well again !

Mental illness in microcontrollers